BYPASS=NORMAL, PD=PLL1_ENABLED, CLK_SEL=32_KHZ_OSCILLATOR, NSEL=1, PSEL=1, DIRECT=DISABLED, FBSEL=CCO_OUT, AUTOBLOCK=DISABLED
PLL1 control register
| PD | PLL1 power down 0 (PLL1_ENABLED): PLL1 enabled 1 (PLL1_POWERED_DOWN): PLL1 powered down |
| BYPASS | Input clock bypass control 0 (NORMAL): Normal. CCO clock sent to post-dividers. Use for normal operation. 1 (INPUT_CLOCK): Input clock. PLL1 input clock sent to post-dividers (default). |
| RESERVED | Reserved. Do not write one to this bit. |
| RESERVED | Reserved. Do not write one to these bits. |
| FBSEL | PLL feedback select. 0 (CCO_OUT): CCO out. CCO output is used as feedback divider input clock. 1 (PLL_OUT): PLL out. PLL output clock (clkout) is used as feedback divider input clock. Use for normal operation. |
| DIRECT | PLL direct CCO output 0 (DISABLED): Disabled 1 (ENABLED): Enabled |
| PSEL | Post-divider division ratio P. The value applied is 2xP. 0 (1): 1 1 (PEQ2): 2 (default) 2 (PEQ4): 4 3 (8): 8 |
| RESERVED | Reserved |
| AUTOBLOCK | Block clock automatically during frequency change 0 (DISABLED): Disabled. Autoblocking disabled 1 (ENABLED): Enabled. Autoblocking enabled |
| NSEL | Pre-divider division ratio N 0 (1): 1 1 (NEQ2): 2 2 (NEQ3): 3 (default) 3 (4): 4 |
| RESERVED | Reserved |
| MSEL | Feedback-divider division ratio (M) 00000000 = 1 00000001 = 2 … 11111111 = 256 |
| CLK_SEL | Clock-source selection. 0 (32_KHZ_OSCILLATOR): 32 kHz oscillator 1 (IRC_DEFAULT): IRC (default) 2 (ENET_RX_CLK): ENET_RX_CLK 3 (ENET_TX_CLK): ENET_TX_CLK 4 (GP_CLKIN): GP_CLKIN 5 (RESERVED): Reserved 6 (CRYSTAL_OSCILLATOR): Crystal oscillator 7 (PLL0USB): PLL0USB 8 (PLL0AUDIO): PLL0AUDIO 9 (RESERVED): Reserved 10 (RESERVED): Reserved 12 (IDIVA): IDIVA 13 (IDIVB): IDIVB 14 (IDIVC): IDIVC 15 (IDIVD): IDIVD 16 (IDIVE): IDIVE |
| RESERVED | Reserved |